BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//pretalx//pretalx.kicad.org//kicon-na-2025//NTBUTQ
BEGIN:VTIMEZONE
TZID:PST
BEGIN:STANDARD
DTSTART:20001029T030000
RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10;UNTIL=20061029T100000Z
TZNAME:PST
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
END:STANDARD
BEGIN:STANDARD
DTSTART:20071104T030000
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
END:STANDARD
BEGIN:DAYLIGHT
DTSTART:20000402T030000
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=4;UNTIL=20060402T110000Z
TZNAME:PDT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
END:DAYLIGHT
BEGIN:DAYLIGHT
DTSTART:20070311T030000
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
END:DAYLIGHT
END:VTIMEZONE
BEGIN:VEVENT
UID:pretalx-kicon-na-2025-P9QEBW@pretalx.kicad.org
DTSTART;TZID=PST:20250529T142500
DTEND;TZID=PST:20250529T151000
DESCRIPTION:Designing a PCB is more than just routing and connecting compon
 ents—it's about ensuring your board can be manufactured without expensiv
 e reworks and delays. That's where DRCs come in. They act as a defense aga
 inst design for manufacturing issues\, catching mistakes before they reach
  the fab house. KiCad 9 takes this further with custom DRCs\, ensuring man
 ufacturability from the initial design phase.\nIn this presentation\, you
 ’ll learn how to set up custom DRC in KiCad 9 to prevent critical manufa
 cturing errors.\n\nConfiguring KiCad 9 custom DRC to prevent DFM issues\n\
 nThe updated KiCad 9 DRC engine allows deeper customization\, letting you 
 define rules and match your CM's capabilities. You can set up the constrai
 nts in advance for trace width and drill sizes and eliminate the guessing 
 game.\n\nOne of the common pitfalls in PCB design is violating trace width
  and spacing requirements. If traces are too thin\, they might cause overh
 eating. If they are too close together\, there is a higher risk of short c
 ircuits. To counter this\, set the values in the DRC editor for minimum tr
 ace width and spacing (for example\, 6 mil). \n\nVias and annular rings ar
 e widely prone to manufacturing issues. When via holes or annular ring dim
 ensions are too small\, it might lead to open circuits. Set minimum via si
 zes and annular ring widths to match your PCB fab's drill tolerances. Conf
 igure the DRC as per your drill-to-copper clearance requirements (prefer 8
  mil). Rules for silkscreen and solder mask must be applied to ensure legi
 ble text and adequate mask relief.\n\nInstead of applying length-matching 
 rules for individual traces\, you can create a group and set constraints f
 or preventing signal skew.\n\nDon't forget to validate component placement
  with your DRC. To prevent assembly issues\, define keep-out zones near th
 e board edges and between large components. \n\nConfiguring DRC makes your
  design ready for will make your prototypes ready for production. Use KiCa
 d 9 custom DRC to enforce practical design for manufacturing rules. \n\nWh
 at you’ll learn:\n\n●	What’s new in KiCad 9?\n●	Common DFM issues 
 \n●	Benefits of custom DRCs for DFM compliance\n●	Setting Up custom DR
 C rules in KiCad 9\n○	Creating custom trace width and spacing rules\n○
 	Setting up via and annular ring constraints\n○	Implementing silkscreen 
 and solder mask rules\n○	Validating component placement\n○	Length matc
 hing for a group of signals\n○	Defining rules for specific layers and re
 gions
DTSTAMP:20261016T150359Z
LOCATION:Theater
SUMMARY:How to Avoid Common DFM Issues with KiCad 9 Custom DRCs - Amit Bahl
URL:https://pretalx.kicad.org/kicon-na-2025/talk/P9QEBW/
END:VEVENT
END:VCALENDAR
